The Invention relates generally to the field of semiconductors, and more specifically to a system and a method for testing very high frequency processors, memory devices, and other high speed semiconductor devices.
As semiconductor technology continues to improve, semiconductor devices operate at increasingly higher frequencies and lower cycle times. As cycle times for leading edge semiconductors decrease, the devices used to determine whether such devices are functioning properly, known as testers, must also operate at increasingly high frequencies to provide a meaningful test of the semiconductor device under the conditions it is expected to operate. While the electronic capabilities of the Test Head Electronic Modules have more than kept pace with modem silicon semiconductor devices, the packaging technology interfacing the Device Under Test to the Test Head Electronics has not. This has created a problem where a tester cannot present the electrical environment of the Device In Use to the Device Under Test. The tester cannot, therefore, fully test the Device Under Test as it will be used as a Device In Use.
Current art high performance testers are normally configured much like one shown in FIG. 1. As can be seen form FIG. 1, such a tester consist of a main frame 1, a test head 2, cabling 3 between the main frame 1 and the test head 2, and a means to position said test head in any stable orientation (articulation 4), so that many different pieces of device handling equipment can be interfaced to the test head. Inside the Test Head 2 reside the Test Head Electronics Modules 5 (xe2x80x9cTHEMxe2x80x9d). There are several kinds of Test Head Electronics Modules to support different testing requirements of the multiplicity of devices which the tester is capable of testing. High speed clocking, analog I/O, digital I/O, and Power Supply regulation are just some of the possible Test Head Electronics Modules. The existence of these modules inside the test head facilitate configuration, maintenance, and the ability to be upgraded. Considerable attention has been used in the design, manufacture, packaging, cooling, and construction of the Test Head and its Electronics.
On the tester and inside the test head are disposed the Test Head Electronics Modules 5, depicted in FIG. 2. The THEM are a collection of highly sophisticated electronic circuits for driving and receiving test patterns, controlling and measuring signal timings, and is designed and developed for each line of Testers from any given manufacturer. Each THEM is interfaced to the tester mainframe by a cable 2 and through a bundle of said cables 3. Each THEM is, in turn, connected to the Device Under Test Connector 7, then to the Device Under Test Board 8, and finally to the Device Under Test through a connector 9. FIG. 3 shows the Test Head interfacing with a device handler, while FIG. 4 shows the same tester interfacing to an electron beam device used to measure electrical signals. The flexibility to be interfaced to a multiplicity of test, measurement, and manufacturing equipment, and the ability to be programmed to test a multiplicity of devices through interchangeable Device Under Test Boards, imposes a set of basic requirements on the packaging of the tester and especially of the test head electronics.
Test Head Electronics Modules are typically constructed of high performance Gallium Arsenide (xe2x80x9cGaAsxe2x80x9d) semiconductor materials. GaAs technology can operate at much higher frequencies than silicon semiconductor devices, and can tolerate higher voltage levels than the fastest silicon semiconductor devices can tolerate, and allows the construction of Test Head Electronics Modules with the ability to drive signals fast enough to test even the highest performance silicon semiconductor devices. Current silicon semiconductor technology is not capable of producing devices which can operate at these performance levels. As a result, test head electronics modules are usually constructed of GaAs technologies, and are (in general) capable of much higher performance than the devices they test. Until recently, GaAs Test Head Electronics Modules were sufficiently fast that testing the high speed signals emanating from silicon semiconductor devices could be performed with little respect for the electrical distance the signals had to travel between the Test Head Electronics Modules and the Device Under Test.
The Test Head Electronics Modules operate at very high frequencies at voltage levels above those tolerated by the high speed Device Under Test, and can, thereby, generate a great deal of heat. The Test Head has been carefully designed to deliver carefully regulated power to each Test Head Electronics Module and careful consideration has been given to cooling each Test Head Electronics Module to insure stable, reliable, and sensitive operation, and high performance signal characteristics. Therefore, the cabling 3 contains signal wires, power supply busses, and means to cool the electronics in the Test Head. This cable must not only carry the plethora of signals, power, and cooling, but must also be capable of accommodating the articulation of the Test Head from the fixed position Main Frame.
A Device Under Test must be supplied with power, clocking, and signals in order to function. The Device Under Test may have a large number of signals, a plurality of clock signals, and consume a large amount of power. A different device may have a lesser number of signals, a different plurality of clock signals, and considerably less power. The Test Head, depicted in FIG. 2, accommodates a multiplicity of different devices by relying on replaceable components known as Device Under Test Boards (DUT Boards) 8. These DUT Boards interface to the Test Head by means of the DUT Board Connector 7, and interface to the Device Under Test through the Device Under Test Connector 9. Many testers now support upwards of 1000 signaling pins.
The Test Head has to be as small as possible to most accurately reflect the electrical environment of the Device In Use while testing said device as Device Under Test. But the minimum size of the test head is fixed by the maximum number of signal pins which interface the Test Head Electronic Modules to the Device Under Test through the DUT Board Connector 7. The Test head is as small as practicable given the plethora of design and use requirements. It is this very size which gives rise to the problem the present invention overcomes.
While the electrical distance between the Test Head Electronics Modules and the device under test remains constant as operating frequencies increases, it takes a progressively larger percentage of a cycle time for a signal to traverse the distance from the THEM to the DUT or to traverse the (same) distance from the DUT to the THEM. As long as any particular signal only traverses the connecting wire in one direction (THEM to DUT, or DUT to THEM), the electrical distance between the THEM and the DUT 41 can be compensated by programming the Test Head Electronics Modules to send these signals 43 from an earlier point in time to the Device Under Test 47, and by programming the Test Head Electronics Modules to receive those signals 45 from the Device Under Test at a later point in time 46. But when signals must traverse the connecting wire in both directions, the tester can no longer fully compensate for the increasing delay 44.
In order to fully characterize Devices Under Test, testers must do more than simply drive digital patterns to the DUT and simply receive digital patterns back from the DUT. Testers are called upon to generate carefully controlled output voltage or current levels at carefully positioned moments in time.
The ability to program a plurality of voltage levels for different signals on different wires and carefully controlling the timing of events across all of these interfacing wires allows the tester to be full utilized in solving its electrical distance problem.
Testers are called upon to measure voltages, currents, and when a voltage or current crosses a specified value. Through these measurements the Devices under test can be tested against not just its operating frequency, but also measured for compliance with respect to its electrical specifications. By repeating these measurements over a vast set of operating conditions and timing arrangements, the true window of safe operation of a DUT can be determined, but more importantly, those events and conditions which impair the functioning of the DUT can be isolated, analyzed and used to propose improvements to the design of the device.
It is the independent programmability of voltage, current, time, and levels that give the Test Head Electronics Modules much of its capability. These capabilities are not compromised under the implementation of the current invention.
A tester represents a large investment for a company manufacturing semiconductor devices, therefore, these companies will desire to maximize their ability to keep these testers busy with the work of testing devices. DUT Boards are often replaced between batches of semiconductor devices and new testing programs loaded into the tester pertinent to the next batch of devices to be tested. Therefore, it is common for DUT Boards to be replaced on the tester, and due to the mechanical stresses of being attached and removed from the Test Head these DUT Boards occasionally require maintenance.
Given the myriad of configuration and the requirement for rapid change from one testing configuration to another, Tester Manufactures are reluctant to place Test Head Electronics Modules directly on the Device Under Test Boards. The present invention alleviates this concern of the placement of such electronics so close to the Devices Under Test. The Test Head Electronics Modules can safely reside in the Test Head, and remotely control MOS devices used as nearly ideal switches to enable testing devices in the electrical environment seen by the Device In Use.
Without loss of generality, FIG. 5 shows a highly simplified schematic of a high speed DDR SRAM 19 attached to a high performance processor (CPU 10) in an Devices In Use (xe2x80x9cDIUxe2x80x9d) electrical environment. This is the environment that the designers of this processor and the designers of this SRAM envisioned. In this electrical environment, each interfacing wire is short, and thereby has a low transit time 21. In order to use the data bus 14 in a bidirectional manner, the currently enabled driver must be turned off, a period of time must exist where neither driver is enabled, and then the other driver can be enabled. Therefore, to change the direction of signal flow (DUT to THEM, or THEM to DUT) the bus 14 must not be driven by either the processor 10 nor the DDR SRAM 20 for short intervals of time 24, 25 and 26. After the last unit of data 27 is driven from the DDR SRAM and received by the processor, the processor waits an amount of time 25 before sending new information to the DDDR SRAM 23. Reliable operation of the bus occurs when the turn around intervals 24, 25, and 26 remain positive units of time. The low latency electrical environment of allow these two Devices In Use to operate reliably.
Again without loss of generality, FIG. 6 shows this same high speed DDR SDRAM 19 attached to a current art high performance tester 30 in the typical electrical environment found on a current art tester. A person of ordinary skill in the art will immediately see that this environment has a necessarily longer transit time 40. The higher latency electrical environment of the Device Under Test makes one of the bus turn around events 44 impossible to achieve. The last unit of information 46-R3 from the DDR SRAM 19 is still arriving when the first unit of information 43-W4 must be driven by the Test Head Electronics Modules 30. The prior art tester is not capable of operating the Device Under Test in the electrical environment of the Device In Use.
It has therefore become desirable to develop a new method and system for presenting the In Use electrical environment to the Device Under Test, to allow for testing semiconductor devices at very high frequencies, as accomplished by the present invention.
The present invention allows a tester to operate the Device Under Test much more like the Device In Use, and, thereby, allow the tester to more fully characterize these high speed devices. FIG. 7 shows the present invention in its most abstract form. A switch 60 on the DUT Board placed close to the DUT Socket 34 and is controlled from the tester 61 and avoids any signal interference 64 by utilizing a plurality of signaling wires 65 and 66. The close placement of this switch to the DUT re-establishes the small electrical environment 68 for the Data Bus 67 of the Device In Use and allows the tester to fully characterize the Device Under Test. The switch must be capable of opening and closing faster than the smallest unit of information transferred.